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LTC1417 Low Power 14-Bit, 400ksps Sampling ADC Converter with Serial I/O
FEATURES
s s s s s s s s s s s s
DESCRIPTIO
16-Pin Narrow SSOP Package (SO-8 Footprint) Sample Rate: 400ksps 1.25LSB INL and 1LSB DNL Max Power Dissipation: 20mW (Typ) Single Supply 5V or 5V Operation Serial Data Output No Missing Codes Over Temperature Power Shutdown: Nap and Sleep External or Internal Reference Differential High Impedance Analog Input Input Range: 0V to 4.096V or 2.048V 81dB S/(N + D) and - 95dB THD at Nyquist
The LTC (R)1417 is a low power, 400ksps, 14-bit A/D converter. This versatile device can operate from a single 5V or 5V supplies. An onboard high performance sample-andhold, a precision reference and internal trimming minimize external circuitry requirements. The low 20mW power dissipation is made even more attractive with two userselectable power shutdown modes. The LTC1417 converts 0V to 4.096V unipolar inputs when using a 5V supply and 2.048V bipolar inputs when using 5V supplies. DC specs include 1.25LSB INL, 1LSB DNL and no missing codes over temperature. Outstanding AC performance includes 81dB S/(N + D) and 95dB THD at a Nyquist input frequency of 200kHz. The internal clock is trimmed for 2s maximum conversion time. A separate convert start input and a data ready signal (BUSY) ease connections to FIFOs, DSPs and microprocessors.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
s s s s s
High Speed Data Acquisition Digital Signal Processing Isolated Data Acquisition Systems Audio and Telecom Processing Spectrum Instrumentation
EQUIVALE T BLOCK DIAGRA
5V 10F 16 LTC1417 AIN+ AIN- 1 2 S/H 14-BIT ADC 14 VDD
A 400kHz, 14-Bit Sampling A/D Converter in a Narrow 16-Lead SSOP Package Effective Bits and Signal-to-(Noise + Distortion) vs Input Frequency
14 12 86 80 74 68
EFFECTIVE BITS
6 SERIAL PORT 7 8 9
REFCOMP 10F
4
4.096V BUFFER
EXTCLKIN SCLK CLKOUT DOUT
VREF 1F
3
8k
2.5V REFERENCE
TIMING AND LOGIC
14 BUSY 12 RD 13 CONVST 11 SHDN
1417 TA01
5
AGND
15
VSS 10 (0V OR - 5V)
DGND
U
10 8 6 4 2 1k 10k 100k INPUT FREQUENCY (Hz) 1M
1417 TA02
W
U
U
62
1
S/(N + D) (dB)
LTC1417 ABSOLUTE
(Notes 1, 2)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW AIN+ AIN- VREF REFCOMP AGND EXTCLKIN SCLK CLKOUT 1 2 3 4 5 6 7 8 16 VDD 15 VSS 14 BUSY 13 CONVST 12 RD 11 SHDN 10 DGND 9 DOUT
Positive Supply Voltage (VDD) .................................. 6V Negative Supply Voltage (VSS) Bipolar Operation Only .......................... - 6V to GND Total Supply Voltage (VDD to VSS) Bipolar Operation Only ....................................... 12V Analog Input Voltage (Note 3) Unipolar Operation .................. - 0.3V to (VDD + 0.3V) Bipolar Operation............ (VSS - 0.3) to (VDD + 0.3V) Digital Input Voltage (Note 4) Unipolar Operation ............................... - 0.3V to 10V Bipolar Operation.........................(VSS - 0.3V) to 10V Digital Output Voltage Unipolar Operation ................... - 0.3 to (VDD + 0.3V) Bipolar Operation........... (VSS - 0.3V) to (VDD + 0.3V) Power Dissipation ............................................. 500mW Operating Temperature Range LTC1417C .............................................. 0C to 70C LTC1417I ............................................ - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
ORDER PART NUMBER LTC1417ACGN LTC1417CGN LTC1417AIGN LTC1417IGN GN PART MARKING 1417A 1417 1417AI 1417I
GN PACKAGE 16-LEAD (NARROW) PLASTIC SSOP
TJMAX = 110C, JA = 95C/W
Consult factory for Military grade parts.
CO VERTER CHARACTERISTICS
PARAMETER Resolution No Missing Codes Integral Linearity Error Differential Linearity Error Transition Noise Offset Error Full-Scale Error Full-Scale Tempco (Note 12) External Reference (Note 8) Internal Reference External Reference = 2.5V (Note 7) CONDITIONS
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. Specifications are measured while using the internal reference unless otherwise noted. (Notes 5, 6)
MIN
q q q q
LTC1417 TYP MAX
LTC1417A MIN TYP MAX 14 14
UNITS Bits Bits
14 13 0.8 0.33 2 0.7 1.5 5 15 5 15 5 20 60 30
0.5 1.25 0.35 0.33 2 15 5 10 20 1 10 60 15 1
LSBRMS LSB LSB LSB ppm/C ppm/C ppm/C
q
IOUT(REF) = 0, Internal Reference, 0C TA 70C IOUT(REF) = 0, Internal Reference, - 40C TA 85C IOUT(REF) = 0, External Reference
A ALOG I PUT
SYMBOL PARAMETER VIN IIN
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS 4.75V VDD 5.25V (Unipolar) 4.75V VDD 5.25V, - 5.25V VSS - 4.75V (Bipolar) CONVST = High
q q q
MIN
TYP 0 to 4.096 2.048
MAX
UNITS V V
Analog Input Range (Note 9) Analog Input Leakage Current
1
2
U
LSB LSB A
W
U
U
WW
W
U
U
U
LTC1417
A ALOG I PUT
SYMBOL PARAMETER CIN tACQ tAP tjitter CMRR
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS Between Conversions (Sample Mode) During Conversions (Hold Mode)
q
Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Time Sample-and-Hold Aperture Time Jitter Analog Input Common Mode Rejection Ratio
DY A IC ACCURACY The q indicates specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25C. (Note 5)
SYMBOL S/(N + D) THD SFDR IMD PARAMETER Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth S/(N + D) 77dB CONDITIONS 100kHz Input Signal 100kHz Input Signal, First Five Harmonics 200kHz Input Signal fIN1 = 97.3kHz, fIN2 = 104.6kHz
q q
I TER AL REFERE CE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance CONDITIONS IOUT = 0 IOUT = 0, 0C TA 70C IOUT = 0, - 40C TA 85C 4.75V VDD 5.25V - 5.25V VSS - 4.75V 0.1mA |IOUT| 0.1mA
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
MIN
q
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL PARAMETER VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage High-Z Output Leakage DOUT, CLKOUT High-Z Output Capacitance DOUT, CLKOUT Output Source Current Output Sink Current CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
MIN
q q q
U
U
U
U
WU
U
U
MIN
TYP 14 3 150 -1.5 5
MAX
UNITS pF pF
500
ns ns psRMS dB dB
0V < (AIN+ = AIN-) < 4.096V (Unipolar) - 2.048V < (AIN+ = AIN-) < 2.048V (Bipolar)
65 65
MIN 79 - 85
TYP 81 - 95 - 98 - 97 10 0.8
MAX
UNITS dB dB dB dB MHz MHz
U
TYP 2.500 10 20 0.05 0.05 8
MAX 2.520
UNITS V ppm/C ppm/C LSB/V LSB/V k
2.480
TYP
MAX 0.8 10
UNITS V V A pF V V
2.4
1.4 VDD = 4.75V, IO = - 10A VDD = 4.75V, IO = - 200A VDD = 4.75V, IO = 160A VDD = 4.75V, IO = - 1.6mA VOUT = 0V to VDD, RD High RD High (Note 9) VOUT = 0V VOUT = VDD 4.74
q q q q
4.0 0.05 0.10 0.4 10 15 - 10 10
V V A pF mA mA
3
LTC1417
POWER REQUIRE E TS
SYMBOL PARAMETER VDD VSS IDD Positive Supply Voltage (Notes 10, 11) Negative Supply Voltage (Note 10) Positive Supply Current Nap Mode Sleep Mode ISS Negative Supply Current Nap Mode Sleep Mode Power Dissipation
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS Bipolar Only (VSS = 0V for Unipolar) Unipolar, RD High (Note 5) Bipolar, RD High (Note 5) SHDN = 0V, RD = 0V SHDN = 0V, RD = 5V Bipolar, RD High (Note 5) SHDN = 0V, RD = 0V SHDN = 0V, RD = 5V Unipolar Bipolar
q q
PDIS
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
SYMBOL fSAMPLE(MAX) tCONV tACQ tACQ + tCONV t1 t2 t3 t4 t5 t6 t7 PARAMETER Maximum Sampling Frequency Conversion Time Acquisition Time Acquisition Plus Conversion Time SHDN to CONVST Wake-Up Time from Nap Mode CONVST Low Time CONVST to BUSY Delay Data Ready Before BUSY Delay Between Conversions Wait Time RD After BUSY Data Access Time After RD CL = 25pF
q
TI I G CHARACTERISTICS
t8 t9 t10 t11 t12 fSCLK fEXTCLKIN tdEXTCLKIN
Bus Relinquish Time RD Low Time CONVST High Time Delay Time, SCLK to DOUT Valid Time from Previous Data Remain Valid After SCLK Shift Clock Frequency External Conversion Clock Frequency Delay Time, CONVST to External Conversion Clock Input (Note 9) CL = 25pF CL = 25pF (Note 13)
4
UW
MIN 4.75 - 4.75
TYP
MAX 5.25 - 5.25
UNITS V V mA mA A A mA A nA mW mW
4.0 4.3 750 0.1 2.0 0.7 1.5 20.0 31.5
5.5 6.0
q
2.8
q q
27.5 44
UW
CONDITIONS
q q q q
MIN 400
TYP 1.8 150 2.1 500
MAX 2.25 500 2.5
UNITS kHz s ns s ns ns
(Note 10) (Notes 10, 11) CL = 25pF CL = 25pF (Note 10)
q q q q q
40 35 7 250 -5 15 20 30 40 40 55 35 t7 40 15 5 0 0.05 10 20 9 20 40 12 70
ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz s
CL = 100pF
q q q q q q q q q
LTC1417
The q indicates specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
SYMBOL tH SCLK tL SCLK tH EXTCLKIN tL EXTCLKIN PARAMETER SCLK High Time SCLK Low Time EXTCLKIN High Time EXTCLKIN Low Time CONDITIONS (Note 9) (Note 9)
q q q q
TI I G CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND and AGND wired together (unless otherwise noted). Note 3: When these pin voltages are taken below VSS or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA without latchup if the pin is driven below VSS (ground for unipolar mode) or above VDD. Note 4: When these pin voltages are taken below VSS they will be clamped by internal diodes. This product can handle input currents greater than 100mA below VSS without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, VSS = - 5V, fSAMPLE = 400kHz, tr = tf = 5ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a singleended AIN+ input with AIN- grounded.
TYPICAL PERFOR A CE CHARACTERISTICS
Typical INL Curve
1.0
1.0
SIGNAL/(NOISE + DISTORTION) (dB)
0.5 DNL ERROR (LSBs) INL (LSBs)
0
-0.5
-1.0 0 4096 8192 OUTPUT CODE
1417 G01
12288
UW
UW
MIN 10 10 0.04 0.04
TYP
MAX
UNITS ns ns
20 20
s s
Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from - 0.5LSB when the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: The falling CONVST edge starts a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For best results ensure that CONVST returns high either within 625ns after conversion start or after BUSY rises. Note 12: Typical RMS noise at the code transitions. See Figure 2 for histogram. Note 13: t11 of 40ns maximum allows fSCLK up to 10MHz for rising capture with 50% duty cycle. fSCLK up to 20MHz for falling capture with 5ns setup time.
(TA = 25C) S/(N + D) vs Input Frequency and Amplitude
90 80 70 60 50 40 30 20 10 0 1k 100k 10k INPUT FREQUENCY (Hz) 1M
1417 G03
Differential Nonlinearity vs Output Code
VIN = 0dB
0.5
VIN = -20dB
0
VIN = -60dB
- 0.5
-1.0
16384
0
4096
12288 8192 OUTPUT CODE
16384
1417 G02
5
LTC1417 TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25C)
Signal-to-Noise Ratio vs Input Frequency
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
90 80
SIGNAL-TO-NOISE RATIO (dB)
SPURIOUS FREE DYNAMIC RANGE (dB)
70 60 50 40 30 20 10 0 1k 10k 100k INPUT FREQUENCY (Hz) 1M
1417 G04
Nonaveraged, 4096 Point FFT, Input Frequency = 10kHz
0 -20 fSAMPLE = 400kHz fIN = 10.05859375kHz SFDR = -97.44dB SINAD = 81.71dB 0
AMPLITUDE (dB)
AMPLITUDE (dB)
-40 -60 -80
AMPLITUDE (dB)
-40 -60 -80
-100 -120
0
50
100 150 FREQUENCY (kHz)
Power Supply Feedthrough vs Ripple Frequency
0
COMMON MODE REJECTION (dB)
60 50 40 30 20 10 0
CHANGE IN OFFSET VOTLAGE (LSB)
VRIPPLE = 60mV fSAMPLE = 400kHz 20 fIN = 200kHz FEEDTHROUGH (dB) 40 60 80 VSS 100 120 1k 10k 100k 1M RIPPLE FREQUENCY (Hz) 10M
1417 G10
VDD DGND
6
UW
Distortion vs Input Frequency
0 - 20 - 40 - 60 - 80 THD -100 3RD -120 2ND 1 10 100 INPUT FREQUENCY (kHz) 1000
1417 G05
Spurious-Free Dynamic Range vs Input Frequency
0 -20 -40 -60 -80 -100 -120 1k 10k 100k INPUT FREQUENCY (Hz) 1M
1417 G06
Nonaveraged, 4096 Point FFT, Input Frequency = 200kHz
fSAMPLE = 400kHz fIN = 197.949188kHz -20 SFDR = -98dB SINAD = 81.1dB 0
Intermodulation Distortion Plot
fSAMPLE = 400kHz fIN1 = 97.303466kHz - 20 fIN2 = 104.632568kHz VIN = 4.096VP-P - 40 - 60 - 80
-100 -120
-100 -120 0 50 100 150 FREQUENCY (kHz) 200
1417 G08
200
1417 G07
0
20 40 60 80 100 120 140 160 180 200 FREQUENCY (kHz)
1417 G09
Input Common Mode Rejection vs Input Frequency
70 10 9 8 7 6 5 4 3 2 1 0 1 100 10 INPUT FREQUENCY (kHz) 1000
1417 G11
Input Offset Voltage Shift vs Source Resistance
1
100 1k 10k 100k 10 INPUT SOURCE RESISTANCE ()
1M
1417 G12
LTC1417 TYPICAL PERFOR A CE CHARACTERISTICS (TA = 25C)
VDD Supply Current vs Temperature (Unipolar Mode)
6 5 4 3 2 1 0 -75 -50 -25 6 5 4 3 2 1 0 -75 -50 -25
VDD SUPPLY CURRENT (mA)
VDD SUPPLY CURRENT (mA)
VSS SUPPLY CURRENT (mA)
0 25 50 75 100 125 150 TEMPERATURE (C)
1417 G14
0 25 50 75 100 125 150 TEMPERATURE (C)
1417 G13
VDD Supply Current vs Sampling Frequency (Unipolar Mode)
5.0 4.5
VDD SUPPLY CURRENT (mA) VDD SUPPLY CURRENT (mA)
5.0 4.5
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 50 100 150 200 250 300 350 400 450 500 SAMPLING FREQUENCY (kHz)
1417 G16
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 50 100 150 200 250 300 350 400 450 500 SAMPLING FREQUENCY (kHz)
1417 G17
VSS SUPPLY CURRENT (mA)
4.0
PIN FUNCTIONS
AIN+ (Pin 1): Positive Analog Input. AIN- (Pin 2): Negative Analog Input. VREF (Pin 3): 2.50V Reference Output. Bypass to AGND with 1F. REFCOMP (Pin 4): 4.096V Reference Output. Bypass to AGND using 10F tantalum in parallel with 0.1F ceramic. AGND (Pin 5): Analog Ground. EXTCLKIN (Pin 6): External Conversion Clock Input. A 5V input will enable the internal conversion clock. SCLK (Pin 7): Data Clock Input. CLKOUT (Pin 8): Conversion Clock Output. DOUT (Pin 9): Serial Data Output. DGND (Pin 10): Digital Ground. SHDN (Pin 11): Power Shutdown Input. Low selects shutdown. Shutdown mode selected by RD. RD = 0V for Nap mode and RD = 5V for Sleep mode. RD (Pin 12): Read Input. This enables the output drivers. RD also sets the shutdown mode when SHDN goes low. RD and SHDN low selects the quick wake-up Nap mode, RD high and SHDN low selects Sleep mode.
UW
VDD Supply Current vs Temperature (Bipolar Mode)
3.0 2.5 2.0 1.5 1.0 0.5
VSS Supply Current vs Temperature (Bipolar Mode)
0 -75 -50 -25
0 25 50 75 100 125 150 TEMPERATURE (C)
1417 G15
VDD Supply Current vs Sampling Frequency (Bipolar Mode)
2.5
VSS Supply Current vs Sampling Frequency (Bipolar Mode)
4.0
2.0
1.5
1.0
0.5
0
0
50 100 150 200 250 300 350 400 450 500 SAMPLING FREQUENCY (kHz)
1417 G18
U
U
U
7
LTC1417
PIN FUNCTIONS
CONVST (Pin 13): Conversion Start Signal. This active low signal starts a conversion on its falling edge. BUSY (Pin 14): The BUSY output shows the converter status. It is low when a conversion is in progress. VSS (Pin 15): Negative Supply, -5V for Bipolar Operation. Bypass to AGND using 10F tantalum in parallel with 0.1F ceramic. Analog ground for unipolar operation. VDD (Pin 16): 5V Positive Supply. Bypass to AGND with 10F tantalum in parallel with 0.1F ceramic.
TEST CIRCUITS
Load Circuits for Access Timing
5V 1k DOUT 1k DGND A) HI-Z TO VOH AND VOL TO VOH CL DOUT CL DGND B) HI-Z TO VOL AND VOH TO VOL
1417 TC01
FUNCTIONAL BLOCK DIAGRA
AIN+ 1
CSAMPLE 16 CSAMPLE AIN- VREF 2 3 8k 2.5V REF ZEROING SWITCHES 15
REF AMP
14-BIT CAPACITIVE DAC
REFCOMP (4.096V) AGND DGND
4 5 10 INTERNAL CLOCK MUX SUCCESSIVE APPROXIMATION REGISTER 14 SHIFT REGISTER 9 7 CONTROL LOGIC DOUT SCLK
6 EXTCLKIN
11 SHDN
8
W
U
U
U
U
U
Load Circuits for Output Float Delay
5V 1k DOUT 1k 30pF DOUT 30pF
A) VOH TO HI-Z
B) VOL TO HI-Z
1417 TC02
VDD VSS (0V FOR UNIPOLAR MODE -5V FOR BIPOLAR MODE)
+
COMP
-
13 CONVST
12 RD
8
14
1417 BD
CLKOUT BUSY
LTC1417
APPLICATIONS INFORMATION
CONVERSION DETAILS The LTC1417 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 14-bit serial output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs (please refer to Digital Interface section for the data format). Conversion start is controlled by the CONVST input. At the start of the conversion, the successive approximation register (SAR) is reset. Once a conversion cycle has begun, it cannot be restarted. During the conversion, the internal differential 14-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the AIN+ and AIN- inputs are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a minimum delay of 500ns will provide enough time for the sampleand-hold capacitors to acquire the analog signal. During the convert phase, the comparator zeroing switches open, placing the comparator in compare mode. The input switches connect the CSAMPLE capacitors to ground, transferring the differential analog input charge onto the summing junction. This input charge is successively compared with the binary weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the differential DAC output balances the AIN+ and AIN- input charges. The SAR contents (a 14-bit data word) that represent the difference of AIN+ and AIN- are output through the serial pin DOUT. DC Performance One way of measuring the transition noise associated with a high resolution ADC is to use a technique where a DC signal is applied to the input of the ADC and the resulting output codes are collected over a large number of conversions. For example in Figure 2, the distribution of output code is shown for a DC input that has been digitized 4096 times. The distribution is Gaussian and the RMS code transition is about 0.33LSB.
4000 3500 3000 2500
COUNTS
AIN+
SAMPLE
CSAMPLE HOLD
+
ZEROING SWITCHES HOLD
AIN-
SAMPLE
CSAMPLE- HOLD CDAC+
HOLD
+
VDAC+ CDAC- COMP
-
VDAC- 14 SAR SHIFT REGISTER
Figure 1. Simplified Block Diagram
U
W
U
U
2000 1500 1000 500 0 -2 -1 0 CODE
1417 F02
1
2
Figure 2. Histogram for 4096 Conversions
DYNAMIC PERFORMANCE The LTC1417 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used to test the ADC's frequency response, distortion and noise performance at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC's spectral content can be examined for frequencies beyond the fundamental. Figure 3 shows a typical LTC1417 FFT plot.
DOUT
1417 F01
9
LTC1417
APPLICATIONS INFORMATION
0 -20 fSAMPLE = 400kHz fIN = 10.05859375kHz SFDR = -97.44dB SINAD = 81.71dB
AMPLITUDE (dB)
-40 -60 -80
-100 -120
0
50
100 150 FREQUENCY (kHz)
200
1417 G07
Figure 3a. LTC1417 Nonaveraged, 4096 Point FFT, Input Frequency = 10kHz
EFFECTIVE BITS
fSAMPLE = 400kHz fIN = 197.949188kHz -20 SFDR = -98dB SINAD = 81.1dB
0
AMPLITUDE (dB)
-40 -60 -80
-100 -120
0
50
100 150 FREQUENCY (kHz)
200
1417 G08
Figure 3b. LTC1417 Nonaveraged, 4096 Point FFT, Input Frequency = 200kHz
Signal-to-Noise Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 3b shows a typical spectral content with a 400kHz sampling rate and a 200kHz input. The dynamic performance is excellent for input frequencies up to and beyond the Nyquist limit of 200kHz.
10
U
W
U
U
Effective Number of Bits The effective number of bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: ENOB (N) = [S/(N + D) - 1.76]/6.02 where N is the effective number of bits of resolution and S/(N + D) is expressed in dB. At the maximum sampling rate of 400kHz, the LTC1417 maintains near ideal ENOBs up to the Nyquist input frequency of 200kHz (refer to Figure 4).
14 12 10 8 6 4 2 1k 10k 100k INPUT FREQUENCY (Hz) 1M
1417 TA02
86 80 74 68 62
S/(N + D) (dB)
Figure 4. Effective Bits and Signal/(Noise + Distortion) vs Input Frequency
Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as:
V22 + V32 + V42 + ...Vn2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. THD vs Input Frequency is shown in Figure 5. The LTC1417 has good distortion performance up to the Nyquist frequency and beyond. THD = 20Log
LTC1417
APPLICATIONS INFORMATION
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
0 - 20 - 40 - 60 - 80 THD -100 3RD -120 2ND 1 10 100 INPUT FREQUENCY (kHz) 1000
1417 G05
Figure 5. Distortion vs Input Frequency
Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. For example, 2nd order IMD terms include (fa fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd-order IMD products can be expressed by the following formula:
fSAMPLE = 400kHz fIN1 = 97.303466kHz - 20 fIN2 = 104.632568kHz VIN = 4.096VP-P
AMPLITUDE (dB)
0
- 40 - 60 - 80
-100 -120 0
20 40 60 80 100 120 140 160 180 200 FREQUENCY (kHz)
1417 G09
Figure 6. Intermodulation Distortion Plot
U
W
U
U
IMD fa + fb = 20Log
(
)
Amplitude at fa fb Amplitude at fa
(
)
Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. Full-Power and Full-Linear Bandwidth The full-power bandwidth is the input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB from a full-scale input signal. The full-linear bandwidth is the input frequency at which the S/(N + D) has dropped to 77dB (12.5 effective bits). The LTC1417 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter's Nyquist Frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. DRIVING THE ANALOG INPUT The differential analog inputs of the LTC1417 are easy to drive. The inputs may be driven differentially or as a singleended input (i.e., the AIN- input is grounded). The AIN+ and AIN- inputs are sampled at the same instant. Any unwanted signal that is common to both inputs will be reduced by the common mode rejection of the sampleand-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC1417 inputs can be driven directly. As source impedance increases, so will acquisition time (see Figure 7). For minimum acquisition time, with high source impedance, a buffer amplifier must be used. The only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts -- 500ns for full throughput rate.
11
LTC1417
APPLICATIONS INFORMATION
100
ACQUISITION TIME (s)
10
1
0.1
0.01 1 10 100 1k 10k SOURCE RESISTANCE () 100k
1417 F07
Figure 7. tACQ vs Source Resistance
Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, choose an amplifier that has a low output impedance (<100) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of 1 and has a closed-loop bandwidth of 10MHz, then the output impedance at 10MHz must be less than 100. The second requirement is that the closed-loop bandwidth must be greater than 10MHz to ensure adequate small-signal settling for full throughput rate. If slower op amps are used, more settling time can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC1417 will depend on the application. Generally, applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC1417. More detailed information is available in the Linear Technology Databooks and on the LinearViewTM CD-ROM. LT 1354: 12MHz, 400V/s Op Amp. 1.25mA maximum supply current. Good AC and DC specifications. Suitable for dual supply application. LT1357: 25MHz, 600V/s Op Amp. 2.5mA maximum supply current. Good AC and DC specifications. Suitable for dual supply application.
LinearView is a trademark of Linear Technology Corporation.
(R)
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LT1360: 50MHz Voltage Feedback Amplifier. 3.8mA supply current, 2.5V to 15V supplies. High AVOL, 1mV offset and 80ns settling to 1mV (4V step, inverting and noninverting configurations) make it suitable for fast DC applications. Excellent AC specifications. Dual and quad versions are available as LT1361 and LT1362. LT1468: 90MHz Voltage Feedback Amplifier. 5V to 15V supplies. Lower distortion and noise. Settles to 0.01% in 770ns. Distortion is -115dB to 20kHz. LT1498/LT1499: 10MHz, 6V/s, Dual/Quad Rail-to-Rail Input and Output Op Amps. 1.7mA supply current per amplifier. 2.2V to 15V supplies. Good AC performance, input noise voltage = 12nV/Hz (typ). LT1630/LT1631: 30MHz, 10V/s, Dual/Quad Rail-to-Rail Input and Output Precision Op Amps. 3.5mA supply current per amplifier. 2.7V to 15V supplies. Best AC performance, input noise voltage = 6nV/Hz (typ), THD = - 86dB at 100kHz. LT1813: Dual 100MHz 750V/s 3mA VFA. 5V to 5V supplies. Distortion is - 86dB to 100kHz and - 77dB to 1MHz with 5V supplies (2VP-P into 500). Great part for fast AC applications with 5V supplies. Input Filtering The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1417 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 10MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 8 shows a 1000pF
100 ANALOG INPUT 1000pF 1 2 3 4 10F 5 AIN+ AIN- VREF LTC1417
REFCOMP AGND
1417 F08
Figure 8. RC Input Filter
LTC1417
APPLICATIONS INFORMATION
capacitor from + AIN to ground and a 100 source resistor to limit the input bandwidth to 1.6MHz. The 1000pF capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling glitch sensitive circuitry. High quality capacitors and resistors should be used since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. Input Range The 2.048V and 0V to 4.096V input ranges of the LTC1417 are optimized for low noise and low distortion. Most op amps also perform well over these ranges, allowing direct coupling to the analog inputs and eliminating the need for special translation circuitry. Some applications may require other input ranges. The LTC1417 differential inputs and reference circuitry can accommodate other input ranges often with little or no additional circuitry. The following sections describe the reference and input circuitry and how they affect the input range. INTERNAL REFERENCE The LTC1417 has an on-chip, temperature compensated, curvature corrected, bandgap reference which is factory trimmed to 2.500V. It is internally connected to a reference amplifier and is available at Pin 3. An 8k resistor is in series with the output so that it can be easily overdriven in applications where an external reference is required, see Figure 9. A capacitor must be connected between the
5V 1 5V VIN VOUT LT1460-2.5 10F ANALOG INPUT 2.5V 2 3 4 0.1F 5 VDD
OUTPUT CODE
OUTPUT CODE
AIN+ AIN-
LTC1417 VREF REFCOMP AGND
1417 F09
Figure 9. Using the LT1460 as an External Reference
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reference amplifier compensation pin (REFCOMP, Pin 4) and ground. The reference is stable with capacitors of 1F or greater. For the best noise performance, a 10F in parallel with a 0.1F ceramic is recommended. The VREF pin can be driven with a DAC or other means to provide input span adjustment. The reference should be kept in the range of 2.25V to 2.75V for specified linearity. UNIPOLAR / BIPOLAR OPERATION AND ADJUSTMENT Figure 10a shows the input/output characteristics for the LTC1417. The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, ... FS - 1.5LSB). The output code is natural binary with 1LSB = FS/16384 = 4.096V/16384 = 250V. Figure 10b shows the input/output transfer characteristics for the bipolar mode in two's complement format.
111...111 111...110 111...101 111...100 1LSB = FS = 4.096V 16384 16384
000...011 000...010 000...001 000...000 0V
UNIPOLAR ZERO
1 LSB INPUT VOLTAGE (V)
FS - 1LSB
1417 F10a
Figure 10a. LTC1417 Unipolar Transfer Characteristics
011...111 011...110 BIPOLAR ZERO
000...001 000...000 111...111 111...110
100...001 100...000 -FS/2
FS = 4.096V 1LSB = FS/16384 -1 0V 1 LSB LSB INPUT VOLTAGE (V) FS/2 - 1LSB
1417 F10b
Figure 10b. LTC1417 Bipolar Transfer Characteristics
13
LTC1417
APPLICATIONS INFORMATION
Unipolar Offset and Full-Scale Error Adjustment In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset error must be adjusted before full-scale error. Figures 11a and 11b show the extra components required for fullscale error adjustment. Zero offset is achieved by adjusting the offset applied to the AIN- input. For zero offset error, apply 125V (i.e., 0.5LSB) at the input and adjust the offset at the AIN- input until the output code flickers between 0000 0000 0000 00 and 0000 0000 0000 01. For full-scale adjustment, an input voltage of 4.095625V (FS - 1.5LSBs) is applied to AIN+ and R2 is adjusted until the output code flickers between 1111 1111 1111 10 and 1111 1111 1111 11. Bipolar Offset and Full-Scale Error Adjustment Bipolar offset and full-scale errors are adjusted in a similar fashion to the unipolar case using the circuit in Figure 11b. Again, bipolar offset error must be adjusted before full-scale error. Bipolar offset error adjustment is achieved by adjusting the offset applied to the AIN- input. For zero offset error, apply - 125V (i.e., - 0.5LSB) at AIN+ and adjust the offset at the AIN- input until the output code flickers between 0000 0000 0000 00 and 1111 1111 1111 11. For full-scale adjustment, an input voltage of 2.047625V (FS - 1.5LSBs) is applied to AIN+ and R2 is adjusted until the output code flickers between 0111 1111 1111 10 and 0111 1111 1111 11. BOARD LAYOUT AND GROUNDING To obtain the best performance from the LTC1417, a printed circuit board with ground plane is required. The ground plane under the ADC area should be as free of breaks and holes as possible, such that a low impedance path between all ADC grounds and all ADC decoupling capacitors is provided. It is critical to prevent digital noise from being coupled to the analog input, reference or analog power supply lines. Layout should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track. An analog ground plane separate from the logic system ground should be established under and around the ADC. Pin 5 (AGND) and Pin 10 (DGND) and all other analog grounds should be connected to this single analog ground plane. The REFCOMP bypass capacitor and the VDD bypass capacitor should also be connected to this analog ground plane. No other digital grounds should be connected to this analog ground plane. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and the foil width for these tracks should be as wide as possible. In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a
R8 100 ANALOG INPUT OFFSET R1 ADJ 50k
R7 48k 1 AIN+ AIN- VREF
5V VDD
R3 24k R5 FS R2 47k ADJ 50k
R4 100
2 3
LTC1417
R6 24k 10F 0.1F
4 5
REFCOMP AGND V SS
1417 F11a
Figure 11a. Offset and Full-Scale Adjust Circuit If - 5V Is Not Available
-5V ANALOG INPUT OFFSET R1 ADJ 50k R3 24k FS R2 R5 47k ADJ 50k R6 24k 10F 0.1F R4 100 1 2 3 4 5 AIN+ AIN- VREF
5V VDD
LTC1417
REFCOMP AGND V SS
1417 F11b
-5V
Figure 11b. Offset and Full-Scale Adjust Circuit If - 5V Is Available
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LTC1417
APPLICATIONS INFORMATION
1 AIN+ AIN- ANALOG INPUT CIRCUITRY VREF 3 1F REFCOMP 4 10F 2 LTC1417 AGND 5 VSS 15 10F VDD 16 10F DGND 10 DIGITAL SYSTEM
+ -
ANALOG GROUND PLANE
1417 F12
Figure 12. Power Supply Grounding Practice
wait state during conversion or by using three-state buffers to isolate the ADC data bus. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC1417 has differential inputs to minimize noise coupling. Common mode noise on the AIN+ and AIN- leads will be rejected by the input CMRR. The AIN- input can be used as a ground sense for the AIN+ input; the LTC1417 will hold and convert the difference voltage between AIN+ and AIN-. The leads to AIN+ (Pin 1) and AIN- (Pin 2) should be kept as short as possible. In applications where this is not possible, the AIN+ and AIN- traces should be run side by side to equalize coupling. SUPPLY BYPASSING High quality, low series resistance ceramic, 10F bypass capacitors should be used at the VDD and REFCOMP pins. Surface mount ceramic capacitors such as Taiyo Yuden LMK325BJ106MN provide excellent bypassing in a small board space. Alternatively 10F tantalum capacitors in parallel with 0.1F ceramic capacitors can be used. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible.
SHDN t1 CONVST
Figure 14. SHDN to CONVST Wake-Up Timing
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Example Layout Figures 13a, 13b, 13c and 13d show the schematic and layout of a suggested evaluation board. The layout demonstrates the proper use of decoupling capacitors and ground plane with a 2-layer printed circuit board. POWER SHUTDOWN The LTC1417 provides two power shutdown modes, Nap and Sleep, to save power during inactive periods. The Nap mode reduces ADC power dissipation by 80% and leaves only the digital logic and reference powered up. The wake-up time from Nap to active is 500ns (see Figure 14). In Sleep mode, all bias currents are shut down and only leakage current remains-- about 2A. Wake-up time from Sleep mode is much slower since the reference circuit must power up and settle to 0.005% for full 14-bit accuracy. Sleep mode wake-up time is dependent on the value of the capacitor connected to the REFCOMP (Pin 4). The wake-up time is 30ms with the recommended 10F capacitor. Shutdown is controlled by Pin 11 (SHDN); the ADC is in shutdown when it is low. The shutdown mode is selected with Pin 12 (RD); low selects Nap mode, high selects Sleep mode.
1417 F14
15
LTC1417
APPLICATIONS INFORMATION
C1 0.1F 5A C2 0.1F
7 3
+ -
4
5 6 1 8 OPTIONAL
2 JP1 R3 75
U3 LT1363CN8
J1 BNC
JP2 R1 10k
C4 0.1F
J2 BNC R2 10k JP3 C6 1F
R4 75
C3 1000pF 50V
U1 LTC1417CGN 1 2 3 4 +AIN -AIN VREF REFCOMP AGND EXTCLKIN SCK CLKOUT VDD VSS BUSY CONVST RD SHDN DGND DOUT
+
+
C7 10F 16V
+
5 6 7 8
JP5A JP5B JP5C 8
Figure 13a. Suggested Evaluation Circuit Schematic
Figure 13b. Suggested Evaluation Circuit Board--Component Side Silkscreen
Figure 13c. Suggested Evaluation Circuit Board--Component Side
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+ -
4
5 6 1 8
E1 5V
+
2
U4 LT1363CS8
5A C10 10F 16V
E2 GND AGND DGND -5A JP7 U2A TC74HCT244AF 2 1 18 E3 -5V
C5 0.1F
C8 5A 10F 16V
C9 10F 16V
-5A 16 15 14 13 12 11 10 9 5A JP4 R5 100k JP6 6 4
19 U2B 3 U2C 1 16 19 5 U2E 1 14 19 7 U2G 1 12 19 9 C12 0.1F 5A BYPASS CAPACITOR FOR U2 1 19 1 19 1 19 1 19 17
+
-5A C11 10F 16V J3 BNC
U2D 15 5A
R6 100k U2F 13
R8 100k BUSY RD DOUT SCLK
J8 CON7 1 2 3 4 5 6 7
1417 F13a
U2H 11 R7 100k
CLKOUT EXTCLKIN
Figure 13d. Suggested Evaluation Circuit Board--Solder Side
LTC1417
APPLICATIONS INFORMATION
DIGITAL INTERFACE The LTC1417 operates in serial mode. The RD control input is common to all peripheral memory interfacing. Only four digital interface lines are required, SCLK, CONVST, EXTCLKIN and DOUT. SCLK, the serial data shift clock can be an external input or supplied by the LTC1417's internal clock. Internal Clock The ADC has an internal clock. Either the internal clock or an external clock may be used as the conversion clock (see Figure 15). The internal clock is factory trimmed to achieve a typical conversion time of 1.8s, and a maximum conversion time over the full operating temperature range of 2.5s. No external adjustments are required, and with the guaranteed maximum acquisition time of 0.5s, throughput performance of 400ksps is assured. Conversion Control Conversion start is controlled by the signal applied to the CONVST input. A falling edge on the signal applied to the CONVST pin starts a conversion. Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output. BUSY is low during a conversion. Data Output Output will be active when RD is low. A high RD will threestate the ouput. In unipolar mode (VSS = 0V), the data will be in straight binary format (corresponding to the unipolar input range). In bipolar mode (VSS = - 5V), the data will be in two's complement format (corresponding to the bipolar input range). Serial Output Mode Conversions are started by a falling CONVST edge. After a conversion is completed and the output shift register has been updated, BUSY will go high and valid data will be available on DOUT (Pin 9). This data can be clocked out either before the next conversion starts or it can be clocked out during the next conversion. To enable the serial data output buffer and shift clock, RD must be low. Figure 15 shows a function block diagram of the LTC1417. There are two pieces to this circuitry: the conversion clock selection circuit (EXTCLKIN and CLKOUT) and the serial port (SCLK, DOUT and RD).
*** DATA IN 14 CLOCK INPUT SHIFT REGISTER 7 12 SCLK RD
SAR
16 CONVERSION CLOCK CYCLES THREE STATE BUFFER 8
EOC CLOCK DETECTOR INTERNAL CLOCK
Figure 15. Functional Block Diagram
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DATA OUT THREE STATE BUFFER
9
DOUT
CLKOUT
***
6
EXTCLKIN
14
BUSY
1417 F15
17
LTC1417
APPLICATIONS INFORMATION
Conversion Clock Selection In Figure 15, the conversion clock controls the internal ADC operation. The conversion clock can be either internal or external. By connecting EXTCLKIN high, the internal clock is selected. This clock generates 16 clock cycles which feed into the SAR for each conversion. To select an external conversion clock, apply an external conversion clock to EXTCLKIN (Pin 6). (When an external shift clock (SCLK) is used during a conversion, the SCLK should be used as the external conversion clock to avoid the noise generated by the asynchronous clocks. To maintain accuracy, the external conversion clock frequency must be between 50kHz and 9MHz.) The SAR sends an end of conversion signal, EOC, that gates the external conversion clock so that only 16 clock cycles can go into the SAR, even if the external clock, EXTCLKIN, contains more than 16 cycles. When RD is low, these 16 cycles of conversion clock (whether internally or externally generated) will appear on CLKOUT during each conversion and then CLKOUT will remain low until the next conversion. If desired, CLKOUT can be used as a master clock to drive the serial port. Because CLKOUT is running during the conversion, it is important to avoid excessive loading that can cause large supply transients and create noise. For the best performance, limit CLKOUT loading to 20pF. Serial Port The serial port in Figure 15 is made up of a 16-bit shift register and a three-state output buffer that are controlled by two inputs: SCLK and RD. The serial port has one output, DOUT, that provides the serial output data. The SCLK is used to clock the shift register. Data may be clocked out with the internal conversion clock operating as a master by connecting CLKOUT (Pin 8) to SCLK (Pin 7) or with an external data clock applied to SCLK. The minimum number of SCLK cycles required to transfer a data word is 14. Normally, SCLK contains 16 clock cycles for a word length of 16 bits; 14 bits with MSB first, followed by two trailing zeros. A logic high on RD disables SCLK and three-states DOUT. In case of using a continuous SCLK, RD can be controlled to limit the number of shift clocks to the desired number (i.e., 16 cycles) and to three-state DOUT after the data transfer. In power shutdown mode (SHDN = low), a high RD selects Sleep mode while a low RD selects Nap mode. DOUT outputs the serial data; 14 bits, MSB first, on the falling edge of each SCLK (see Figures 16 and 17). If 16 SCLKs are provided, the 14 data bits will be followed by two zeros. The MSB (D13) will be valid on the first rising and the first falling edge of the SCLK. D12 will be valid on the second rising and the second falling edge as will all the remaining bits. The data may be captured using either edge. The largest hold time margin is achieved if data is captured on the rising edge of SCLK. BUSY gives the end-of-conversion indication. When the LTC1417 is configured as a serial bus master, BUSY can be used as a framing pulse. To three-state the serial port after transferring the serial output data, BUSY and RD should be connected together at the ADC (see Figure 17). Figures 17 to 20 show several serial modes of operation, demonstrating the flexibility of the LTC1417 serial interface.
SCLK
DOUT
1417 F16
Figure 16. SCLK to DOUT Delay
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LTC1417
APPLICATIONS INFORMATION
Serial Data Output During a Conversion Using Internal Clock for Conversion and Data Transfer. Figure 17 shows data from the previous conversion being clocked out during the conversion with the LTC1417 internal clock providing both the conversion clock and the SCLK. The internal clock has been optimized for the fastest conversion time; consequently, this mode can provide the best overall speed performance. To select the internal conversion clock, tie EXTCLKIN (Pin 6) high. The internal clock appears on CLKOUT (Pin 8) which can be tied to SCLK (Pin 7) to supply the SCLK.
CONVST
13
CONVST
(SAMPLE N) EXTCLKIN = 5 CONVST t10 t3 BUSY (= RD) t7 1 CLKOUT (= SCLK) t4 DOUT Hi-Z D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FILL ZEROS D13 Hi-Z D13 D12 DATA N t8 CLKOUT (= SCLK)
1417 F17
t2
2
3
4
5
6
VIL t11 t12
DOUT
D13
Figure 17. Internal Conversion Clock Selected. Data Transferred During Conversion Using the ADC Clock Output as a Master Shift Clock (SCLK Driven from CLKOUT)
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BUSY RD
14 12
BUSY (= RD) P OR DSP (CONFIGURED AS SLAVE) OR SHIFT REGISTER
LTC1417 SCLK CLKOUT DOUT 8 9
7 CLKOUT ( = SCLK) DOUT
(SAMPLE N + 1)
t5 HOLD SAMPLE HOLD
7
8
9
10
11
12
13
14
15
16
1
2
3
D11
DATA (N - 1) tCONV
D12 CAPTURE ON RISING CLOCK CAPTURE ON FALLING CLOCK
D11
VOH VOL
19
LTC1417
APPLICATIONS INFORMATION
Using External Clock for Conversion and Data Transfer. In Figure 18, data from the previous conversion is output during the conversion with an external clock providing both the conversion clock and the shift clock. To select an external conversion clock, apply the clock to EXTCLKIN. The same clock is also applied to SCLK to provide a data shift clock. To maintain conversion accuracy, the external clock frequency must be between 50kHz and 9MHz. Using an external clock to transfer data while an internal clock controls the conversion process is not recommended. As both signals are asynchronous, clock noise can corrupt the conversion result.
CONVST
13
CONVST
(SAMPLE N) t2 CONVST t10 t3 BUSY (= RD) tdEXTCLKIN 1 EXTCLKIN (= SCLK) t7 DOUT Hi-Z D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FILL ZEROS t4 D13 Hi-Z D13 D12 DATA N t8 EXTCLKIN (= SCLK) tLEXTCLKIN VIL t11 t12 DOUT D13 D12 CAPTURE ON RISING CLOCK CAPTURE ON FALLING CLOCK D11 VOH VOL tHEXTCLKIN
1417 F18
2
3
4
5
6
Figure 18. External Conversion Clock Selected. Data Transferred During Conversion Using the External Clock (External Clock Drives Both EXTCLKIN and SCLK)
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BUSY RD
14 12 6 7 9
BUSY (= RD)
LTC1417 EXTCLKIN SCLK DOUT
EXTCLKIN ( = SCLK)
P OR DSP
DOUT
(SAMPLE N + 1)
t5 HOLD SAMPLE HOLD
7
8
9
10
11
12
13
14
15
16
1
2
3
D11
DATA (N - 1) tCONV
LTC1417
APPLICATIONS INFORMATION
Serial Data Output After a Conversion Using an Internal Conversion Clock and an External Data Clock. In this mode, data is output after the end of each conversion and before the next conversion is started (Figure 19). The internal clock is used as the conversion clock and an external clock is used for the SCLK. This mode is useful in applications where the processor acts as a serial bus master device. This mode is SPI and MICROWIRETM compatible. It also allows operation when the SCLK frequency is very low (less than 30kHz). To select the internal conversion clock, tie EXTCLKIN high. The external SCLK is applied to SCLK. RD can be used to gate the external SCLK, such that data will clock only after RD goes low and to three-state DOUT after data transfer. If more than 16 SCLKs are provided, more zeros will be filled in after the data word indefinitely.
MICROWIRE is a trademark of National Semiconductor Corporation.
CONVST
13
CONVST
BUSY RD
LTC1417 SCLK DOUT 9 7
EXTCLKIN = 5 CONVST
t2
t3 BUSY HOLD t6 RD 1 SCLK t7 DOUT (SAMPLE N) tCONV DATA N Hi-Z D13 12 11 10 9 8 7 2 3 4 5 6 7
Figure 19. Internal Conversion Clock Selected. Data Transferred After Conversion Using an External SCLK. BUSY Indicates End of Conversion
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INT C0 P OR DSP SCK MISO
t10 t5 SAMPLE t9
8
9 10 11 12 13 14 15 16
t8 6 5 4 3 2 1 0 FILL ZEROS Hi-Z
1417 F19
SCLK VIL
t LSCLK t HSCLK t11 t12
DOUT
D13
D12 CAPTURE ON RISING CLOCK CAPTURE ON FALLING CLOCK
D11
VOH VOL
21
LTC1417
APPLICATIONS INFORMATION
Using an External Conversion Clock and an External Data Clock. In Figure 20, data is also output after each conversion is completed and before the next conversion is started. An external clock is used for the conversion clock and either another or the same external clock is used for the SCLK. This mode is identical to Figure 19 except that an external clock is used for the conversion. This mode allows the user to synchronize the A/D conversion to an external clock either to have precise control of the internal bit test timing or to provide a precise conversion time. As in Figure 19, this mode works when the SCLK frequency is very low (less than 30kHz). However, the external conversion clock must be between 30kHz and 9MHz to maintain accuracy. If more than 16 SCLKs are provided, more zeros will be filled in after the data word indefinitely. To select the external conversion clock, apply an external conversion clock to EXTCLKIN. The external SCLK is applied to SCLK. RD can be used to gate the external SCLK such that data will be clocked out only after RD goes low.
CONVST
13
CONVST EXTCLKIN BUSY LTC1417 RD SCLK DOUT 9
tdEXTCLKIN 1 EXTCLKIN t2 CONVST
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
t3 BUSY HOLD t6 RD 1 SCLK t7 DOUT (SAMPLE N) tCONV DATA N Hi-Z D13 12 11 10 9 8 7 2 3 4 5 6 7
Figure 20. External Conversion Clock Selected. Data Transferred After Conversion Using an External SCLK. BUSY Indicates End of Conversion
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CLKOUT INT P OR DSP
12 7
C0 SCK MISO
1
2
3
4
t4
t10 t5 SAMPLE t9
8
9 10 11 12 13 14 15 16
t8 6 5 4 3 2 1 0 FILL ZEROS Hi-Z
SCLK VIL
t LSCLK t HSCLK t11 t12
DOUT
D13
D12 CAPTURE ON RISING CLOCK CAPTURE ON FALLING CLOCK
D11
VOH VOL
1417 F20
LTC1417
TYPICAL APPLICATIONS
Figure 21 shows the connections necessary for interfacing the LTC1417 and LTC1391 8-channel signal acquisition system to an SPI port. With the sample software routine shown in Listing A, the SPI uses MOSI to send serial data to the LTC1391 8-channel multiplexer, selecting one of eight MUX channels. While data is sent to the LTC1391, SPI uses MISO to retrieve conversion data from the LTC1417. After the data transfer is complete, the conversion start signal is sent to the LTC1417. The end of conversion is signaled by a logic high on the BUSY output. When this occurs, data is exchanged between the LTC1417/LTC1391 and the controller. The timing diagram in Figure 22 shows the relation between MUX channel selection data and the conversion data that are simultaneously exchanged. There is a two conversion delay between the MUX data selects a given channel and when that channel's data is retrieved.
IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8
1 2 3 4 5 6 7 8
S0 S1 LTC1391 S2 S3 S4 S5 S6 S7
V+ D V- DOUT DIN CS CLK DGND
Figure 21. 0V to 4.096V, 8-Channel Data Acquisition System Configured for Control and Data Retrieval by a 68HC11 C. Code is Shown in Listing A
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5V 0.1F 16 15 1F 14 10F 13 12 11 10 9 NC 5V NC 4 5 6 7 8 3 1 2 AIN+ AIN- VREF REFCOMP AGND EXTCLKIN SCLK CLKOUT VDD VSS BUSY CONVST RD SHDN DGND DOUT 16 15 14 13 12 11 10
5V 10F
LTC1417
PORT C, BIT 7 PORT C, BIT 0 SS
MC68HC11 9 MISO CLK MOSI
1417 F21
23
LTC1417
TYPICAL APPLICATIONS
Listing A
*********************************************************************** * * * This example program retrieves data from a previous LTC1417 * * conversion and loads the next LTC1391 MUX channel. It stores the * * 14-bit, right justified data in two consecutive memory locations. * * It finishes by initiating the next conversion. * * * *********************************************************************** * ************************************ * 68HC11 register definitions * ************************************ * PIOC EQU $1002 Parallel I/O control register * "STAF,STAI,CWOM,HNDS, OIN, PLS, EGA,INVB" PORTC EQU $1003 Port C data register * "Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0" DDRC EQU $1007 Port D data direction register * "Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0" * 1 = output, 0 = input PORTD EQU $1008 Port D data register * " - , - , SS* ,CSK ;MOSI,MISO,TxD ,RxD " DDRD EQU $1009 Port D data direction register SPCR EQU $1028 SPI control register * "SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0" SPSR EQU $1029 SPI status register * "SPIF,WCOL, - ,MODF; - , - , - , - " SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter * * RAM variables to hold the LTC1417's 14 conversion result * DIN1 EQU $00 This memory location holds the LTC1417's bits 13 - 08 DIN2 EQU $01 This memory location holds the LTC1417's bits 07 - 00 MUX EQU $02 This memory location holds the MUX address data * ******************************************* * Start GETDATA Routine * ******************************************* * ORG $C000 Program start location INIT1 LDAA #$03 0,0,0,0,0,0,1,1 * "STAF=0,STAI=0,CWOM=0,HNDS=0, OIN=0, PLS=0, EGA=1,INVB=1" STAA PIOC Ensures that the PIOC register's status is the same * as after a reset, necessary of simple Port D manipulation LDAA #$01 0,0,0,0,0,0,0,1 * "Bit7=input,- ,- ,- ,- ,- ,- ,Bit0=output" * Bit7 used for BUSY signal input, Bit0 used for CONVST * signal output STAA DDRC The direction of PortD's bits are now set LDAA PORTC Get contents of Port C ORAA #%00000001 Set Bit0 high STAA PORTC Initialize CONVST to a logic high LDAA #$2F -,-,1,0;1,1,1,1 * -, -, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X STAA PORTD Keeps SS* a logic high when DDRD, bit 5 is set LDAA #$38 -,-,1,1;1,0,0,0 STAA DDRD SS* , SCK, MOSI are configured as Outputs * MISO, TxD, RxD are configured as Inputs * DDRD's bit 5 is a 1 so that port D's SS* pin is a general output LDAA #$50 STAA SPCR The SPI is configured as Master, CPHA = 0, CPOL = 0 * and the clock rate is E/2
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LTC1417
TYPICAL APPLICATIONS
* (This assumes an E-Clock frequency of 4MHz. For higher * E-Clock frequencies, change the above value of $50 to a * value that ensures the SCK frequency is 2MHz or less.) GETDATAPSHX PSHY PSHA * ***************************************** * Setup indecies * ***************************************** * LDX #$0 The X register is used as a pointer to the memory * locations that hold the conversion data LDY #$1000 * ***************************************** * The next short loop ensures that the * * LTC1417's conversion is finished * * before starting the SPI data transfer * ***************************************** * CONVENDLDAA PORTC Retrieve the contents of port D ANDA #%10000000 Look at Bit7 * Bit7 = Hi; the LTC1417's conversion is complete * Bit7 = Lo; the LTC1417's conversion is not * complete BPL CONVEND Branch to the loop's beginning while Bit7 remains * low * ************************************************************************* * This routine sends data to the LTC1417 and sets its MUX channel. The * * very first time this routine is entered produces invalid data. Each * * time thereafter, the data will correspond to the previous active * * CONVST signal sent to the LTC1417. * ************************************************************************* * LDAA #$00 Dummy value for upper byte of 16-bit SPI transfer BCLR PORTD,Y %00100000 This sets the SS* output bit to a logic * low, selecting the LTC1417 STAA SPDR Transfer Accum. A contents to SPI register to initiate * serial transfer WAITMX1 LDAA SPSR Get SPI transfer status BPL WAITMX1If the transfer is not finished, read status LDAA SPDR Load accumulator A with the current byte of LTC1417 data * that was just received STAA DIN1 Transfer the LTC1417's high byte (Bit13 - Bit6) to memory LDAA MUX Retrieve MUX address ORAA #$08 Set the MUX's ENABLE bit STAA SPDR Transfer Accum. A contents to SPI register to initiate * serial transfer WAITMX2 LDAA SPSR Get SPI transfer status BPL WAITMX2If the transfer is not finished, read status BSET PORTD,Y %00100000 This sets the SS* output bit to a logic * high, de-selecting the LTC1417 LDAA SPDR Load accumulator A with the current byte of LTC1417 data * that was just received STAA DIN2 Transfer the LTC1417's low byte (Bit5 - Bit0) to memory LDD DIN1 Load the contents of DIN1 and DIN2 into the double * accumulator D LSRD LSRD Two logical shifts to the right to right justify the * 14-bit conversion results STD DIN1 Place right justified result back in memory
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25
LTC1417
TYPICAL APPLICATIONS
* ***************************************** * Initiate a LTC1417 conversion * ***************************************** * BCLR PORTC,Y %00000001 This sets PORTC, Bit0 output to a logic * low, initiating a conversion BSET PORTC,Y %00000001 This resets PORTC, Bit0 output to a logic * high, returning CONVST to a logic high * PULA Restore the A register PULY Restore the Y register PULX Restore the X register RTS
CONVST
BUSY
RD
MUX DATA
CH1
CH2
ADC DATA
CH7
CH0
MUX OUT
1417 F22
CH0
CH1
Figure 22. This Diagram Shows the Relationship Between the Selected LTC1391 MUX Channel and the Conversion Data Retrieved from the LTC1417 When Using the Sample Program in Listing A. At Any Point in Time, a Two Conversion Delay Exists Between the Selected MUX Channel and When Its Data Is Retrieved
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CH3
CH4
CH5
CH1
CH2
CH3
CH2
CH3
CH4
LTC1417
TYPICAL APPLICATIONS
Figure 23 uses the DG408 to select one of eight 2.048V bipolar signals and apply it to the LTC1417's analog input. The circuit is designed to connect to a 68HC11 C. The MUX's parallel input is connected to the controller's port C and the LTC1417's serial interface is accessed through the controller's SPI interface. The sequence to generate a conversion is shown in sample program Listing B. The first step selects a MUX channel. This is followed by initiating a conversion and waiting for BUSY to go high, signifying end of conversion. Once BUSY goes low, the SPI is used to retrieve the 14-bit conversion data. The timing relationships between the various control signals and data transmission are shown in Figure 24.
IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8
1 2 3 4 5 6 7 8
S1 S2 DG408 S3 S4 S5 S6 S7 S8
V+ V- GND EN A2 A1 A0 D
13 3 14 2 0.1F 10F 1F
Figure 23. With an Input Range of 2.048V for Each of Eight Inputs, This Data Acquisition System is Configured for Communication with the 68HC11 C
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5V
- 5V
5V
- 5V
0.1F 1 2 3 4 5 5V 6 7 NC 8 AIN+ AIN- VREF REFCOMP AGND EXTCLKIN SCLK CLKOUT VDD VSS BUSY CONVST RD SHDN DGND DOUT 16 15 14 13 12 11 10 9 SS MISO MC68HC11 CLK PORT C, BIT 2 PORT C, BIT 1 PORT C, BIT 0
1417 F23
LTC1417
PORT C, BIT 7 PORT C, BIT 6
27
LTC1417
TYPICAL APPLICATIONS
Listing B
************************************************************************* * * * This example program selects a DG408 MUX channel using parallel * * port C, initiates a conversion, and retrieves data from the LTC1417. * * It stores the 14-bit, right justified data in two consecutive memory * * locations. * * * ************************************************************************* * ***************************************** * 68HC11 register definitions * ***************************************** * PIOC EQU $1002 Parallel I/O control register * "STAF,STAI,CWOM,HNDS, OIN, PLS, EGA,INVB" PORTC EQU $1003 Port C data register * "Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0" DDRC EQU $1007 Port D data direction register * "Bit7,Bit6,Bit5,Bit4,Bit3,Bit2,Bit1,Bit0" * 1 = output, 0 = input PORTD EQU $1008 Port D data register * " - , - , SS* ,CSK ;MOSI,MISO,TxD ,RxD " DDRD EQU $1009 Port D data direction register SPCR EQU $1028 SPI control register * "SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0" SPSR EQU $1029 SPI status register * "SPIF,WCOL, - ,MODF; - , - , - , - " SPDR EQU $102A SPI data register; Read-Buffer; Write-Shifter * * RAM variables to hold the LTC1417's 14 conversion result * DIN1 EQU $00 This memory location holds the LTC1417's bits 13 - 08 DIN2 EQU $01 This memory location holds the LTC1417's bits 07 - 00 MUX EQU $02 This memory location holds the MUX address data * ***************************************** * Start GETDATA Routine * ***************************************** * ORG $C000 Program start location INIT1 LDAA #$03 0,0,0,0,0,0,1,1 * "STAF=0,STAI=0,CWOM=0,HNDS=0, OIN=0, PLS=0, EGA=1,INVB=1" STAA PIOC Ensures that the PIOC register's status is the same * as after a reset, necessary of simple Port D manipulation LDAA #$47 0,1,0,0,0,1,1,1 * "Bit7=input,Bit6=output,- ,- ,- ,Bit2=output,Bit1=output, * Bit0=output" * Bit7 used for BUSY input * Bit6 used for CONVST signal output * Bits 2 - 0 are used for the MUX address STAA DDRC Direction of PortD's bit are now set LDAA #$2F -,-,1,0;1,1,1,1 * -, -, SS*-Hi, SCK-Lo, MOSI-Hi, MISO-Hi, X, X STAA PORTD Keeps SS* a logic high when DDRD, Bit5 is set LDAA #$38 -,-,1,1;1,0,0,0 STAA DDRD SS* , SCK, MOSI are configured as Outputs * MISO, TxD, RxD are configured as Inputs * DDRD's Bit5 is a 1 so that port D's SS* pin is a general output LDAA #$50 STAA SPCR The SPI is configured as Master, CPHA = 0, CPOL = 0 * and the clock rate is E/2 * (This assumes an E-Clock frequency of 4MHz. For higher
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LTC1417
TYPICAL APPLICATIONS
* E-Clock frequencies, change the above value of $50 to a * value that ensures the SCK frequency is 2MHz or less.) GETDATAPSHX PSHY PSHA * ***************************************** * Setup indecies * ***************************************** * LDX #$0 The X register is used as a pointer to the memory * locations that hold the conversion data LDY #$1000 * ***************************************** * Initialize the LTC1417's CONVST input * * to a logic high before a conversion * * start * ***************************************** * BSET PORTC,Y %01000000 This sets PORTC, Bit6 output to a logic * high, forcing CONVST to a logic high * ***************************************** * Retrieve the MUX address from memory * * and send it to the DG408 * ***************************************** * LDAA PORTC Capture the contents of PortC ORAA MUX "Add" the MUX address STAA PORTC Select the MUX channel * ***************************************** * Initiate a LTC1417 conversion * ***************************************** * BCLR PORTC,Y %01000000 This sets PORTC, Bit6 output to a logic * low, initiating a conversion BSET PORTC,Y %01000000 This resets PORTC, Bit6 output to a logic * high, returning CONVST to a logic high * ***************************************** * The next short loop ensures that the * * LTC1417's conversion is finished * * before starting the SPI data transfer * ***************************************** * CONVENDLDAA PORTC Retrieve the contents of port D ANDA #%10000000 Look at Bit7 * Bit7 = Hi; the LTC1417's conversion is complete * Bit7 = Lo; the LTC1417's conversion is not * complete BPL CONVEND Branch to the loop's beginning while Bit7 * remains high * ************************************************************************* * This routine sends data to the LTC1417 and sets its MUX channel. The * * very first time this routine is entered produces invalid data. Each * * time thereafter, the data will correspond to the previous active * * CONVST signal sent to the LTC1417. * ************************************************************************* *
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29
LTC1417
TYPICAL APPLICATIONS
BCLR * TRFLP1 LDAA STAA * WAIT1 LDAA * BPL * * LDAA * STAA INX CPX BNE * BSET * LDD * LSRD LSRD * STD PULA PULY PULX RTS This sets the SS* output bit to a logic low, selecting the LTC1417 #$0 Load accumulator A with a null byte for SPI transfer SPDR This writes the byte into the SPI data register and starts the transfer SPSR This loop waits for the SPI to complete a serial transfer/exchange by reading the SPI Status Register WAIT1 The SPIF (SPI transfer complete flag) bit is the SPSR's MSB and is set to one at the end of an SPI transfer. The branch will occur while SPIF is a zero. SPDR Load accumulator A with the current byte of LTC1417 data that was just received 0,X Transfer the LTC1417's data to memory Increment the pointer #DIN2+1Has the last byte been transferred/exchanged? TRFLP1 If the last byte has not been reached, then proceed to the next byte for transfer/exchage PORTD,Y %00100000 This sets the SS* output bit to a logic high, de-selecting the LTC1417 DIN1 Load the contents of DIN1 and DIN2 into the double accumulator D Two logical shifts to right justify the 14-bit conversion results Return right justified data to memory Restore the A register Restore the Y register Restore the X register PORTD,Y %00100000
DIN1
CONVST
BUSY
RD
SCLK
DOUT
CH0 DATA
MUX DATA
CH0
Figure 24. Using the Sample Program In Listing 2, the LTC1417, Combined with the DG408 8-Channel MUX, Has No Latency Between the Selected Input Voltage and Its Conversion Data as Shown In the Timing Relationship Above
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CH5
CH1 DATA
CH2 DATA
CH3 DATA
CH1
CH2
CH3
1417 F24
LTC1417
PACKAGE DESCRIPTIO U
Dimensions in inches (millimeters) unless otherwise noted.
GN Package 16-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.189 - 0.196* (4.801 - 4.978) 16 15 14 13 12 11 10 9
0.009 (0.229) REF
0.229 - 0.244 (5.817 - 6.198)
0.150 - 0.157** (3.810 - 3.988)
1 0.015 0.004 x 45 (0.38 0.10) 0.007 - 0.0098 (0.178 - 0.249) 0.016 - 0.050 (0.406 - 1.270) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0 - 8 TYP 0.053 - 0.068 (1.351 - 1.727)
23
4
56
7
8 0.004 - 0.0098 (0.102 - 0.249)
0.008 - 0.012 (0.203 - 0.305)
0.025 (0.635) BSC
GN16 (SSOP) 0398
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC1417
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
1417fs sn1417 LT/TP 0100 4K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1999

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